教师姓名:胡盛东
邮箱地址:hushengdong@hotmail.com
工作电话:未公开

胡盛东  20027月毕业于四川大学,获工学学士学位,20057月于四川大学获工学硕士学位,20059月-20106月在电子科技大学微电子与固体电子学院学习,获工学博士学位,专业为微电子学与固体电子学。20107月至今在重庆大学通信工程学院从事教学和科研工作。主研参与多项国家级、省部级和横向科研项目的研究工作,在国内外重要学术期刊发表论文20余篇,其中第一作者SCI收录11篇,公开或获权国家专利多项。先后担任了本科生的《微电子器件》、《半导体物理》、《集成电路工艺原理》与《ASIC设计原理与应用》等课堂教学及实验环节的指导工作。

主要研究方向:半导体功率器件及IC设计与应用

主持项目:作为项目承担人主持国家自然科学基金两项,重庆市自然科学基金、中国博士后科学基金面上项目及特别资助项目、中央高校基金等项目多项。

近年主要论著

[1]    Junjie An, and Shengdong Hu. Experimental andTheoretical Demonstration of Temperature Limitation for 4H-SiC MOSFET duringUnclamped Inductive Switching, IEEE Journal of Emerging and Selected Topics in Power Electronics, 2020, 8(1):206-214

[2]    Junjie An, and Shengdong Hu. SiC trench MOSFET with heterojunction diode for lowswitching loss and high short-circuit capability, IET Power Electronics, 2019, 12(8): 1981–1985

[3] Junjie An, and Shengdong Hu. HeterojunctionDiode Shielded SiC Split-Gate Trench MOSFET With Optimized Revere RecoveryCharacteristic and Low Switching Loss,  IEEE Access, 2019, 7: 28592-28596.

[4]      ShengdongHu, Ye Huang, Tao Liu, Jingwei Guo, Jian'an Wang and Jun Luo. A comparative study of a deep-trench superjunction SiC VDMOS device,  Journal  of  Computational  Electronics , 2019, 18(2): 553-560

[5]     Jianmei Lei, ShengdongHu, Dong Yang, Ye Huang, Lidong Chen, Jingwei Guo, Chang Liu, Tao Liu, andYuan Wang. Performance analysis of a novel trench SOI LDMOS with symmetricfloating vertical field plates, Results in Physics, 2019, 12:810-815

[6]     Jingwei Guo, Shengdong Hu, Ye Huang, Qi Yuan, DongYang, Ling Yang, Liang You, and Jianyi Yu. Improved SOI LDMOS performance byusing a partial stepped polysilicon layer as the buried layer, Materials Science in SemiconductorProcessing, 2019, 90: 7-12

[7]    Jianmei Lei, ShengdongHu, DongYang, Ye Huang, Qi Yuan, Jingwei Guo, Linghui Zeng, SiqiWang, and Xuan Yang. Investigation of a novel SOI LDMOS using p+ buried islandsin the drift region by numerical simulations, Journal of ComputationalElectronics, 2018,17(2):646-652

[8]     Dong Yang, Shengdong Hu, Jianmei Lei, Ye Huang, Qi Yuan, Yuyu Jiang,Jingwei Guo, Kun Cheng,  Zhi Lin, XichuanZhou, and Fang Tang. An ultra-low specificon-resistance double-gate  trench  SOI  LDMOS  with  P/N  pillars,   Superlattices  and  Microstructures,  2017(112):269-278

[9]     Kun Cheng, Shengdong Hu, Jianmei Lei, Qi Yuan, Yuyu Jiang, Ye Huang, DongYang, Zhi Lin, Xichuan Zhou, and Fang Tang. A novel trench SOI LDMOS with a dual floatingvertical field plate,Superlattices and Microstructures,2017(109)134-144.

[10]     Dong Yang, Shengdong Hu, Ye Huang, Yuyu Jiang, Kun Cheng, Qi Yuan,Jianmei Lei, Zhi Lin, Xichuan Zhou, and Fang Tang. Ultra-low SpecificOn-Resistance  Trench  SOI  LDMOS  with a Floating Lateral Field Plate. IETE Technical Review, 2018,35(4):342-350

[11]     Kun Cheng, Shengdong Hu, Yuyu Jiang, Qi Yuan, Dong Yang, Ye Huang,                Jianmei Lei, Zhi Lin, XichuanZhou, and Fang Tang. Simulation-based  performance  analysis  of  anultra-low  specific  on-resistance  trench  SOI  LDMOS  with  a  floating  vertical field  plate.  Journal ofComputational Electronics, 2017,16(1):83-89

[12]     Yinhui Chen, Shengdong Hu, Kun Cheng, Yuyu Jiang, Jianlin Zhou, FangTang, Xichuan Zhou, and Ping Gan. Improving breakdown performance for novelLDMOS using n+ floating islands in substrate. ElectronicsLetters,2016,52(8):658-659

[13]    Shengdong Hu*, Jun Luo, YuYu Jiang, KunCheng, Yinhui Chen, Jinging Jin, Jian’an Wang, Jianlin Zhou, Fang Tang, XichuanZhou, and Ping Gan. Improving Breakdown, Conductive, and ThermalPerformances for SOI high voltage LDMOS Using a Partial Compound Buried Layer.Solid-State Electronics, 2016,(117):146-151

[14]     Yinhui Chen, Shengdong Hu, Kun Cheng, YuYu Jiang, Jun Luo, Jian’an Wang,Fang Tang, Xichuan Zhou, Jianlin Zhou, and Ping Gan. A Novel Low Specific On-resistance  Double-gate LDMOS  with Multiple Buried P-layers in the Drift  Region  Basedon  the Silicon-On-Insulator Substrate, Superlattices and Microstructures, 2016(89)59-67

[15] HU Sheng-Dong, JIN Jing-Jing, CHEN Yin-Hui, JIANG Yu-Yu, CHENG Kun,ZHOU Jian-Lin, LIU Jiang-Tao, HUANG Rui, YAO Sheng-Jie. A Novel Interface-Gate  Structure  for  SOI  Power MOSFET to Reduce Specific On-Resistance.Chinese Physics Letters, 2015, 32(9):098502-1-3

[16]     Jingjing Jin, Shengdong Hu, Yinhui Chen, Kaizhou Tan, Jun Luo, Feng Zhou, Zongze Chen, and Ye Huang. ImprovingBreakdown Voltage for a Novel SOI LDMOS with a Lateral Variable Doping Profileon the Top Interface of the Buried Oxide Layer. Advances in Condensed Matter Physics, 2015, Article ID 762498,6 pages.

[17]  ShengdongHu, Yinhui Chen, JingjingJin, Jianlin Zhou, Feng Zhou, ZongzeChen, Ye Huang, Jun Luo, and Jian'an Wang. A Low SpecificOn-Resistance Power Trench MOSFET with a Buried-Interface-Drain. Superlattices and Microstructures, 201585):133-138.